1. Field
This disclosure is generally related to electronic design automation. More specifically, this disclosure is related to methods and apparatuses for generating a floorplan for a circuit design.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in the number of transistors per semiconductor device. This increase in transistor count is empowering computer architects to create digital circuit designs with ever-increasing complexity. As digital circuit designs become more complex, the effort required to place and route circuit elements into a transistor layout also becomes more involved.
In a circuit design flow, a floorplan for the circuit design is usually created before performing detailed placement and routing. The floorplan can specify how the various functional blocks in the circuit design are arranged on the chip. Furthermore, the floorplan is typically used to guide the subsequent placement and routing process.
The process for generating a floorplan is interactive, and requires a number of iterations to refine the floorplan until its characteristics are acceptable. For example, a floorplanning process may require an engineer to iteratively refine the floorplan until the timing and routability characteristics of the floorplan are acceptable.
A single floorplanning iteration can take more than a work day for very large designs. Furthermore, larger circuit designs usually require a larger number of floorplanning iterations.